The Impact of Hardware Models on Shared Memory Consistency Conditions

Shared memory systems provide a contract to the programmer in the form of a consistency condition. The conditions of atomic memory and sequential consistency provide the illusion of a single memory module, as in the uniprocessor case. Weaker conditions improve performance by sacriicing the simple programming model. Consistency conditions are formulated without reference to details of the hardware on which programs execute. We deene the notion of a hardware model, a set of limitations on the communication network (e.g., message delay assumptions) and processing nodes (e.g., amount of available memory). We examine the eeects of several models on a representative set of consistency conditions. In each model, we show how the conditions are related, and show that some are not appropriate for that model. Our study is carried out through relatively complete implementations, state machines which exactly capture the possible behaviors of all implementations in a given model. In addition to elucidating properties of the consistency conditions, these state machines can be used in proofs of correctness, when a particular hardware model is assumed.